A semiconductor memory device driver by a packet command

专利摘要:
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a packet command driven semiconductor memory device employing a multi-bank method, comprising a means for controlling a pass transistor between a global column decoder output line and a pass transistor gate terminal. This cuts off the current path through the local data busline to prevents overall power consumption.
公开号:KR20000065752A
申请号:KR1019990012381
申请日:1999-04-08
公开日:2000-11-15
发明作者:김재형
申请人:김영환；현대전자산업 주식회사；
IPC主号:

专利说明:

A semiconductor memory device driver by a packet command
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet command driven semiconductor memory device, and more particularly, to a packet command driven semiconductor memory which prevents power consumption generated from an unselected bank during a read operation in a multi-bank method simultaneously driven by a global column decoded signal. Relates to a device.
As a packet instruction-driven memory, in particular, the Rambus DRAM employs a multi-bank (8, 16) structure for high-speed input / output of data.
In such a structure, a global column decoder is a signal for driving the pass transistor 10 connecting one bit line pair and one local data bus line pair. In the multi-bank method, as shown in FIG. It is applied to all banks simultaneously to drive the pass transistor 10.
At this time, the operation of the selected bank and the non-selected bank is distinguished. In the conventional method, as described above, the global column decoder signal is simultaneously applied to all banks to drive the pass transistor 10. The bit line pair and the local data bus line pair are interconnected through the turned on pass transistor 10.
Accordingly, unwanted power consumption is caused by the voltage difference between the bit line pair and the local data bus line pair that exist in the precharge state.
In other words, the local data bus line is pre-charged with a voltage of Vdd / 2 and the bit line is precharged with a voltage of Vdd or Vss.Therefore, there is a current path from the bit line to the local data bus line when the word line is driven. Unnecessary power consumption occurs at.
The present invention has been made to solve the above-mentioned problems of the prior art, and means for controlling a pass transistor of an unselected bank by a bank selection signal in a multi-bank method is provided between a pass transistor gate stage and an output line of a global column decoder. It is an object of the present invention to provide a packet instruction driving type semiconductor memory device for preventing unnecessary power consumption by blocking the pass transistor of an unselected bank during a read operation.
According to an aspect of the present invention, there is provided a packet command driving semiconductor memory device including a memory cell array including a plurality of memory elements;
A bit line sense amplifier configured to sense and amplify stored data of the memory cell array transferred through the bit line during word line driving;
A global column decoder for outputting a global column decoder signal for controlling a pass transistor for transferring amplified data of the bit line sense amplifier to a local data bus line during a read operation;
A multi-bank packet instruction driving type semiconductor memory device including a data bus sense amplifier for amplifying amplified data transmitted through a global data bus line connected to the local data bus line and outputting the amplified data to a data output buffer.
Pass transistor control means for turning on the pass transistor of the selected bank and turning off the pass transistor of the unselected bank to control the current path in the unselected bank between the global column decoder output line and the pass transistor gate terminal. It is done.
The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a circuit diagram of a data column path of a conventional semiconductor memory device employing a multi-bank method.
2 is a circuit diagram of a data column path of a packet command driven semiconductor memory device according to the present invention employing a multi-bank method.
3 is a circuit diagram of an application example according to the present invention.
<Explanation of symbols for main parts of drawing>
10: pass transistor 20: pass transistor control unit
FIG. 2 is a circuit diagram of a data column path of a packet command-driven semiconductor memory device in accordance with the present invention employing a multi-bank method, the configuration characteristic of which is a pass transistor 10 connecting a bit line and a local data bus line. The pass transistor controller 20 which is controlled by the bank select signal BK is provided between the gate terminal and the global column decoder output line to control the pass transistor 10 of the unselected bank.
That is, the pass transistor control unit 20 includes an NMOS transistor connected to a gate selection signal BK as a gate and connected between the global column decoder output line and the pass transistor 10 gate terminal, and the pass transistor 10 gate. An NMOS transistor is connected between the terminal and the ground terminal and has a gate connected to the power supply terminal.
In the packet instruction driving type semiconductor memory device according to the present invention adopting the multi-banking structure as described above, even if the global column decoder signal is input to all banks during read operation, in the non-selected bank, the logic low bank selection signal (BK) is used. Since the pass transistor controller 20 is turned off, the global column decoder signal of logic high cannot be applied to the gate terminal of the pass transistor 10.
Therefore, since the pass transistors 10 of all unselected banks are turned off, no current path is formed between the bit lines and the local data bus lines so that power consumption does not occur.
Fig. 3 is a circuit diagram of an application example according to the present invention, taking two pairs of bit lines (bitline0 and / bitline0, bitline1 and / bitline1) and two pairs of local data bus lines (LDB0 and / LDB0, LDB1 and / LDB1). One pass transistor control unit 20 controls two pass transistors 10, and the pass transistor control unit 20 is controlled by a bank selection signal BK.
As described above, the present invention prevents a current path flowing from a bit line of a bank not selected in a shared multi-bank type semiconductor memory device to a local data bus line by using a single global column decoder line to reduce overall power consumption. It is effective to prevent.
In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

权利要求:
Claims (4)
[1" claim-type="Currently amended] A memory cell array comprising a plurality of memory elements,
A bit line sense amplifier configured to sense and amplify stored data of the memory cell array transferred through the bit line during word line driving;
A global column decoder for outputting a global column decoder signal for controlling a pass transistor for transferring amplified data of the bit line sense amplifier to a local data bus line during a read operation;
A multi-bank packet instruction driving type semiconductor memory device including a data bus sense amplifier for amplifying amplified data transmitted through a global data bus line connected to the local data bus line and outputting the amplified data to a data output buffer.
Pass transistor control means for turning on the pass transistor of the selected bank and turning off the pass transistor of the unselected bank to control the current path in the unselected bank between the global column decoder output line and the pass transistor gate terminal. A packet instruction drive type semiconductor memory device.
[2" claim-type="Currently amended] The method of claim 1,
And said pass transistor control means operates on a bank selection signal.
[3" claim-type="Currently amended] The method according to claim 1 or 2,
The pass transistor control means includes: a first MOS transistor connected between a global column decoder output line and a pass transistor gate terminal and to which a bank selection signal is applied to a gate;
And a second MOS transistor connected between the pass transistor gate terminal and a ground terminal and having a gate connected to a power supply terminal.
[4" claim-type="Currently amended] The method of claim 3, wherein
And the first and second MOS transistors include NMOS transistors.

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同族专利:

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公开号 | 公开日

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KR100732287B1|2007-06-25|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1999-04-08|Application filed by 김영환, 현대전자산업 주식회사

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1999-04-08|Priority to KR1019990012381A

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2000-11-15|Publication of KR20000065752A

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2007-06-25|Application granted

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2007-06-25|Publication of KR100732287B1

优先权:

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申请号 | 申请日 | 专利标题

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KR1019990012381A|KR100732287B1|1999-04-08|1999-04-08|A semiconductor memory device driver by a packet command|